Gates of metal-oxide-semiconductor (MOS) transistors receive input signals and transfer output signals in the form of a voltage. The gate oxide can break down if the applied voltage exceeds certain levels. Such excess voltages are often the result of human-operator or mechanical handling operations. Triboelectricity is an electrical charge which evolves when two materials are rubbed together. Human-operators create this type of electricity by walking across a room or by removing an integrated circuit (IC) from its plastic package. Triboelectricity results in a high voltage, which when applied to the pins of an IC package in the form of electrostatic discharge (ESD) can cause breakdown of the gate oxide or overheating due to overcurrent. Such breakdown may cause immediate or expedited destruction of transistors or other devices.
In order to combat problems associated with ESD events, manufacturers of MOS devices design protection devices that provide paths through which to discharge nodes rapidly. Protection devices may be applied between the input buffer or output buffer pads of a device and the respective gates to which they are connected. During an ESD event, a typical protection transistor enters snap-back, a low resistance regime in which large amounts of current are conducted.
Certain processing enhancements, such as siliciding source/drain regions, increase the performance of small-dimension devices, but often negate the benefits of ESD protection. Gate-controlled breakdown structures are easily degradable by silicided (especially self-aligned, silicided, also known as salicided) source/drain regions. Such silicided regions easily melt, or agglomerate, during an ESD event due to their close proximity to the reverse-biased junction (the drain of the MOS transistor in snap-back) edge, which is a source of heat during an ESD event. Attempts have been made to increase the gate-to-contact spacing in ESD protection devices, placing the silicide farther away from the heat-generating area in attempts to minimize the possibility of silicide failure. However, the problem with this solution is that this increased length adds resistance that impedes current which discharges through it. Thus, current tends to flow through the n-channel devices of output buffers first, negating the benefits of the protection device.
Another problem associated with silicided source/drain regions in a protection device is known as the "ballasting" effect. Due to the greatly reduced resistance of silicided regions during an ESD event, the current discharging through the protection device may collapse into a thin filament. This leads to increased heating and earlier device failure.
U.S. Pat. No. 5,021,853 to Mistry teaches an ESD MOS protection device formed by a salicide process. As shown in the prior art FIGS. 1A and 1B, the ESD protection device 11 is formed in part of an IC 10 by an n-channel grounded-gate transistor 11. This device has an output buffer circuit consisting of an n-channel ESD protection transistor 11, an n-channel pull-down transistor 12, and a p-channel pull-up transistor 13. The chip consists of a p(-) epitaxial layer 15 formed on a p(+) substrate 14. P-channel transistors 13 on the chip are formed in n-wells 17 in the epitaxial layer 15. N(+) source/drain regions 18, 19 for the n-channel transistors 12 and for the ESD transistors 11 are implanted into the epitaxial layer 15 and p(+) source/drain regions 21 for the p-channel transistors 13 are implanted into the n-well region 17. Transistor gates 20, 22, 23 are formed of polysilicon overlying a thin gate oxide layer and the channel regions between the source/drain regions 18, 19, 21. The use of sidewall spacers 24, 25 on the sides of the pull-up/pull-down transistors' 12, 13 polysilicon gates 22, 23 provides for self-alignment of the silicided contact areas 26, 27 on the source/drain regions 18, 21. Silicide 28, 29 is also formed on top of the pull-up/pull-down transistors' polysilicon gates 22, 23.
Unlike the other p-channel and n-channel devices, the ESD protection transistor 11 does not have silicided areas on top of the polysilicon gate region 20, nor does it have silicide on the source/drain regions 19 near the gate 20 and self-aligned with the gate 20. Mistry places the silicided source/drain regions 31, 32 of the protection device 11 farther away from the gate 20. While this technique works to minimize silicide failure in the protection device, which leads to its early failure, it does not address the issue that the n-channel device 13 of the output buffer will turn on before the protection device 11 has a chance to shunt the charge away from the internal circuitry. Metal contacts 34, 35, 36, 37 are deposited on top of the silicided source/drain regions 31, 32, 26, 27 in order to connect the devices in the desired circuit configuration. The reason why the n-channel device 13 of the output buffer will turn on first is that its path is less resistive than that through the protection device. By requiring that the gate-to-contact spacing, L, of the protection device 11 be longer than the gate-to-contact spacing of the other transistors in the IC, Mistry creates more resistance in the protection device 11. Thus, current travels through the n-channel device 13 of the output buffer first, where the resistance is lower.
There is a need for an ESD protection device in a MOS IC which prevents an n-channel device of an output buffer from turning on before all of the charge is shunted away through the protection device. There is a further need for preventing ESD charge from reaching input buffer transistors before all of the charge is shunted away through the protection device. Existing techniques do not address these problems. There is a further need for an ESD protection device which utilizes silicided regions in an effective manner, without utilizing salicide techniques, and which exhibit a decreased likelihood of failure. Furthermore, there is a need to increase resistance between output/input buffers of ICs and active devices in ways outside of adjusting the gate-to-contact spacing of structures, such as ESD protection and active devices. While such gate-to-contact spacings may be adjusted to bias discharge through the protection device, there are limitations to the amount of adjustment which is allowable when manufacturing.